A NEW METHODOLOGY FOR DUTY CYCLE CORRECTION IN 90NM ASIC DESIGNS: ANALYSIS AND IMPLEMENTATION

Abstract

This paper presents the analysis and design of a clock signal duty cycle measurement and correction circuit, which is implemented using 90nm ASIC technology. In digital systems, the clock signal plays a crucial role in synchronizing operations across various components. Even minor deviations in the duty cycle can lead to timing violations, setup and hold time failures, increased jitter, and degraded overall performance. Particularly in high-speed and low-power digital circuits, maintaining a 50% duty cycle is critical to ensuring symmetrical timing windows and reducing dynamic power consumption.