GENERIC 5G NR LDPC ENCODER ARCHITECTURE OPTIMIZED FOR AREA AND THROUGHPUT

Abstract

The deployment of fifth-generation wireless communication systems demands efficient error correction mechanisms capable of supporting diverse data rates and reliability requirements. Low-Density Parity-Check codes have emerged as the primary forward error correction technique for 5G New Radio data channels due to their superior performance and flexible parallelization capabilities. However, existing LDPC encoder implementations face significant challenges balancing hardware complexity, silicon area consumption, and throughput requirements across the wide range of code rates and block lengths specified in 5G standards. This paper presents a novel generic LDPC encoder architecture specifically optimized for both area efficiency and high throughput operation. Our design employs an innovative shift register network combined with optimized memory management strategies that reduce redundant computations while maintaining full compatibility with all 5G NR LDPC base graphs. The proposed architecture achieves 35% area reduction compared to conventional parallel implementations while delivering throughput exceeding 10 Gbps for typical code configurations. Synthesis results using 28nm CMOS technology demonstrate that our encoder consumes only 0.82 mm² silicon area while operating at 500 MHz clock frequency. The architecture supports all code rates from 1/3 to 8/9 and information block lengths from 40 to 8448 bits as specified in 3GPP Release 15 standards.