DESIGN AND IMPLEMENTATION OF A LOW-POWER FULL ADDER IN NANOMETER CMOS TECHNOLOGY FOR DIGITAL PROCESSOR APPLICATIONS

Abstract

The growing demand for low-power integrated circuits in nanometer technologies has made power reduction in digital arithmetic units a fundamental design challenge. The full adder, as the most elementary building block of arithmetic logic units and digital processors, plays a central role in determining the energy efficiency of the entire processing system. This study aimed to design, implement, and evaluate a low-power one-bit full adder in nanometer CMOS technology for digital processor applications. Two implementations were simulated using Cadence Virtuoso in the ADE L environment, employing the 90 nm GPDK process at a supply voltage of 1.8 V and an operating temperature of 27°C. The first design was based on standard CMOS logic comprising 36 transistors, and the second was based on the modified gate diffusion input technique comprising 20 transistors. Performance evaluation was conducted based on average power consumption, propagation delay, power-delay product, and occupied area. The results demonstrated that the MGDI design achieved a 61.6% reduction in average power consumption and a 79.6% improvement in propagation delay relative to the standard CMOS implementation. The power-delay product decreased by 92.2%, while transistor count and occupied area were reduced by 44.4% and 51.1%, respectively. Functional correctness was verified across all eight possible input combinations for both designs. These findings indicate that the MGDI technique constitutes an effective approach for low-power full adder design in nanometer CMOS technology and represents a suitable candidate for energy-efficient digital processor applications.