AXI4-LITE UART FIFO DESIGN ON FPGA

Abstract

The design presents the FPGA implementation of a UART data buffering system based on a synchronous FIFO with Axi4-lite interface. The design is for the Cyclone II FPGA development board EP2C5T144 device and was created using Intel Quartus Prime for synthesis and ModelSim for functional simulation, with all RTL written in synthesizable Verilog. A 50 MHz onboard oscillator powers the system, and a baud rate divider CLK_DIV = 434 allows UART operation at 115200 baud. Two 16-deep, 8-bit synchronous FIFOs buffer data between the UART receiver and transmitter, addressing the speed mismatch of serial connection 86.8 µs per byte at 115200 baud and providing data transfer. Functional simulation confirms proper UART framing, FIFO read/write operations, and timing behavior, whereas post-synthesis results demonstrate efficient resource utilization with fewer than 300 logic elements (LEs) and positive temporal slack at 50 MHz. Hardware validation using a USB-to-UART interface confirms reliable real-time data transmission and system stability.