MACHINE LEARNING-DRIVEN VERIFICATION: USING ML TO OPTIMIZE COVERAGE ANALYSIS, PREDICT SIMULATION RUNTIMES, AND AUTO-GENERATE TESTBENCHES.

Abstract

The exponential increase in design complexity of modern System-on-Chip (SoC) and Very Large Scale Integration (VLSI) systems has rendered traditional functional verification methods inadequate due to prolonged simulation times, incomplete coverage closure, and manual testbench development bottlenecks. This paper proposes a machine learning-driven verification (MLDV) framework that addresses these challenges by optimizing coverage analysis, predicting simulation runtimes, and auto-generating testbenches. The proposed methodology leverages supervised learning models—including Random Forest (RF), Gradient Boosting (XGBoost), and Long Short-Term Memory (LSTM) networks—to analyze coverage hole patterns, estimate simulation execution time with high accuracy, and generate synthesizable SystemVerilog testbench components. Experimental evaluations conducted on open-source RISC-V and Tensor Processing Unit (TPU) verification suites demonstrate that the ML-driven approach achieves 96.4% coverage closure acceleration, 94.2% runtime prediction accuracy, and 92.8% testbench generation correctness. The Random Forest model for coverage analysis reduces verification cycles by 42%, while the LSTM-based runtime predictor achieves a Mean Absolute Percentage Error (MAPE) of 5.8%. Auto-generated testbenches attain 89% line coverage within the first three simulation iterations. Results confirm that ML-driven verification significantly enhances productivity, reduces time-to-market, and provides adaptive, intelligent verification flows for next-generation hardware systems.